The increasing complexity of mobile smartphones brings with it new design challenges. While today’s mobile system-on-chip (SoC) devices integrate advanced functionality in an efficient way, they also increase bandwidth requirements to external memory resources. In addition, new features must be implemented without increasing power consumption and negatively impacting battery operating life. To help meet performance, power, and cost requirements, OEMs now have access to next-generation, low-power DDR4 (LPDDR4) technology.
Mobile Device Trends
As mobile smartphones and tablets increasingly replace personal computing clients, mobile system-on-chip (SOC) devices are quickly evolving to enable rapid improvement in mobile compute and graphics performance in response to ever-increasing user-experience expectations. Today, smartphones and tablets make up the backbone of the mobile computing industry. IDC has forecasted that in 2014, worldwide IT spending will grow 5% year over year to $2.1 trillion, most of which will be driven by smartphones and tablets. IDC has also reported that smartphone shipments exceeded 1 billion units in 2013 and are expected to reach 1.7 billion units by 2017.1
As a result of this market growth, smartphones and tablets have become a first-source for leading-edge innovation. Rather than converging existing technologies, new interfaces and features are now introduced in smart phones and trickle down to other applications. Engineers, then, must drive even higher performance and lower power consumption for these mobile devices, setting industry benchmarks for all other platforms.
For example, current high-end smartphones and tablets are being designed with 20+ megapixel cameras with advanced “trick modes” that stitch together the best of multiple photos and eliminate undesirable elements. They also enable multishot, still photography similar to that available in high-end digital still cameras (DSCs), as well as 2k or 4k ultra-HD video recording and editing, which were exclusive to high-end multimedia PCs and workstations just a year ago. These high-end mobile designs feature ultra-HD display capability, 64-bit multicore CPUs, and GPUs that enable 3D graphics. Additionally, smartphones and tablets are benefitting from fast and ubiquitous connectivity enabled by integrated 802.11ac wireless and LTE modems with LAN-like bandwidth.
Many of these features are enabled by highly integrated SoCs that provide greater computing capabilities matched with peripherals like image processors, modems, and Wi-Fi transceivers. This integration has led to a corresponding increase in demand on memory resources and a need for an architecture that can support much higher bandwidth.
Memory bandwidth is not a new problem for mobile devices. Since the introduction of the iPhone, the industry has responded with an evolutionary transition from 2.6 GB/s LPDDR1, to 8.5 GB/s LPDDR2, to 17 GB/s LPDDR3, the technology currently is powering today’s high-end devices in volume production. DRAM bandwidth has roughly doubled with each generation to keep pace with demand.
The next generation of low-power DRAM (LPDRAM)—also known as LPDDR4—addresses these constraints by doubling the bandwidth of LPDDR3 while maintaining power neutrality. For example, LPDDR4 targets 34 GB/s of total bandwidth for a x64 memory subsystem, doubling the bandwidth target from LPDDR3. This bandwidth is achieved by moving to a dual-channel architecture with eight banks per channel—providing more responders for higher efficiency and lower latency—and by using a new high-speed I/O interface capable of up to 4.267 Gb/s.
While mobile SOC capabilities have rapidly increased, the power capacity of mobile systems has stayed relatively static: battery capacities have increased by just a few percentage points over the last decade. Typical battery capacity is 1.4Ah in today’s smartphones and 11.5Ah in tablets. User expectations for active device use are in the 8−10 hour range. Standby device use is equally critical; typically, smartphone designers target 10+ days of standby use while tablets designers target 2+ weeks. The memory device alone can consume up to 30% of the system power in standby mode. In active mode, memory bandwidth is a significant contributor to thermal power consumption as well, contributing 20−25% of the total power used in a typical smartphone using LPDDR3 when heavily utilized.
Another significant power-related constraint on the SOC/memory subsystem in mobile platforms arises from their packaging. Smartphones and tablets are typically sealed systems with no airflow, also known as thermal envelopes. Internal heat sinks move heat away from the SOC/memory subsystem, but their effectiveness is limited since they transfer the heat to the user. In order to prevent burns or fires, system performance is throttled when thermal limits are reached. This results in a negative impact on the user experience in the form of reduced video frame rates, slower processor core clock frequencies, and backlight adjustments.
Several architectural refinements enable LPDDR4 to maintain the same power consumption profile as LPDDR3 while doubling its bandwidth. The x16, dual-channel architecture reduces read/write power while the page size is reduced to 2KB to reduce active power, and the new high-speed, low-swing I/O is tuned to reduce I/O power and improve signal integrity. The LPDDR4 core and I/O supply voltages are decreased to 1.1V (from 1.2V in LPDDR3) to help reduce power consumption. As part of its power neutrality and backward compatibility, LPDDR4 also retains low-power features from its predecessors, including clock start/stop modes, clock frequency change, and power-down, and self-refresh modes.
LPDDR4 keeps system cost down as well by reusing the assembly/packaging technology that is widespread in mobile computing platforms today. LPDDR4 is designed to be packaged in standalone FBGA and PoP packages. Alternatively, it can be combined with Flash devices in MCP and eMCP packages. LPDDR4 also follows the same back-end manufacturing flow as LPDDR3, taking advantage of the same test and burn-in automatic test equipment (ATE). Several new features are included in LPDDR4 to further control costs: masked WRITE commands to enable yield enhancement, a post-package repair option to improve quality, and targeted row refresh to increase reliability.
Keeping the pin count low also helps keep LPDDR4 cost down and reduce overall system complexity. In LPDDR4, the CA bus is reduced to 6 pins from 10 pins in LPDDR3. The LPDDR3 clock scheme is retained in LPDDR4—which includes differential clock and bidirectional differential DQS—also minimizing pin count and enhancing backward compatibility.
Meeting the performance requirements of today’s mobile device while keeping power and cost under control is critical for OEMs. With LPDDR4, systems can have double the bandwidth at the same power profile as LPDDR3, making it the ideal mobile memory technology to power next-generation smartphones and tablets that feature cutting-edge photo and video technology and ultra-HD displays. By keeping costs under control and reusing the same assembly and packaging technologies of previous LPDRAM generations, LPDDR4 helps improve yield, quality, and reliability. LPDDR4 also enables ultra-realistic, console-quality 3D games as well as other exciting new applications in video and photo editing. Consumers everywhere will benefit from LPDDR4 as they buy new smartphones, tablets, and other mobile devices that deliver an incredible user experience.
1. IDC Predictions 2014: Battles for Dominance – and Survival – on the 3rd Platform (Doc #244606), December 2014
Reynette Au is vice president of wireless solutions marketing at Micron Technology.